HOE=0, ERCA=0, EMLM=0, EDBG=0, CX=0, ECX=0, CLM=0, HALT=0
Control Register
| EDBG | Enable Debug 0 (0): When in debug mode, the DMA continues to operate. 1 (1): When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. |
| ERCA | Enable Round Robin Channel Arbitration 0 (0): Fixed priority arbitration is used for channel selection . 1 (1): Round robin arbitration is used for channel selection . |
| HOE | Halt On Error 0 (0): Normal operation 1 (1): Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. |
| HALT | Halt DMA Operations 0 (0): Normal operation 1 (1): Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. |
| CLM | Continuous Link Mode 0 (0): A minor loop channel link made to itself goes through channel arbitration before being activated again. 1 (1): A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. |
| EMLM | Enable Minor Loop Mapping 0 (0): Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. 1 (1): Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. |
| ECX | Error Cancel Transfer 0 (0): Normal operation 1 (1): Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. |
| CX | Cancel Transfer 0 (0): Normal operation 1 (1): Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. |